The present invention relates to open drain type output buffers. FIG. 1(a) illustrates a circuit diagram of an NMOS open-drain type output buffer system. The NMOS open drain type output buffer system 100 includes an NMOS open drain type output buffer 110 having an output pad 120. The output pad 120 is connected via a channel 130 to a power supply Vterm (often called a termination power Vterm) via a termination resistor Rterm. The channel 130 represents, for example, a bus or a portion of a bus, over which a device including the open drain type output buffer 110 and other devices (not shown) communicate.
The NMOS open-drain type output buffer 10 includes a N-type MOS (NMOS) transistor MN. The NMOS transistor MN has its drain coupled to the termination power Vterm via the output pad 120, the channel 130 and the termination resistor Rterm. The NMOS transistor MN has its source coupled to the ground power VSS, and the gate of the NMOS transistor MN is controlled by input data DIN.
When the logic value of the input data DIN is xe2x80x9c1xe2x80x9d and a high input data voltage represents the logic xe2x80x9c1xe2x80x9d state, a pull-down current I flows down from the termination power Vterm (e.g., 1.8V) to ground power VSS (e.g., 1.0V) via the NMOS transistor MN. As a result, an output data DOUT at the output pad 120 and the channel 130 is a low voltage VOL=Vtermxe2x88x92I*Rterm. When the logic value of the input data DIN is xe2x80x9c0xe2x80x9d and a low input data voltage represents the logic xe2x80x9c0xe2x80x9d state, the output data DOUT is a high voltage VOH=Vterm.
FIG. 1(b) shows the voltage level of the input data DIN in relation to the output data DOUT. In this type of open drain output buffer system 100, the low voltage VOL as output data DOUT typically represents a logic xe2x80x9c1xe2x80x9d and the high voltage VOH as output data DOUT typically represents logic xe2x80x9c0xe2x80x9d.
There also exist PMOS output drain buffer systems where a P-type MOS (PMOS) transistor is connected between a high, power supply voltage VDD (e.g., 1.8V) and a low, termination voltage Vterm (e.g., 1.0V). More specifically, the PMOS transistor is connected to the termination voltage Vterm via an output pad, a channel, and a termination resistor Rterm. Here, a low input voltage DIN representing a logic xe2x80x9c0xe2x80x9d produces a low output voltage DOUT also representing a logic xe2x80x9c0xe2x80x9d, and a high input voltage DIN representing a logic xe2x80x9c1xe2x80x9d produces a high output voltage DOUT representing a logic xe2x80x9c1xe2x80x9d.
Unfortunately, open drain type output buffer systems such as discussed above are adversely affected by Intersymbol Interference (ISI). ISI is where previous symbols cause an unwanted variation in the voltage representing successive symbols. As such ISI can result in the erroneous detection of the output data DOUT. FIGS. 2(a), 2(b), 3(a) and 3(b) illustrate examples of the voltage variation in the output data DOUT caused by ISI for the open drain type output buffer system 100 in FIG. 1(a).
FIG. 2(a) shows a voltage variation xcex941 of the output data DOUT caused by ISI when input data DIN transitions from two successive logic xe2x80x9c1xe2x80x9ds to xe2x80x9c0xe2x80x9d. As shown, the channel attenuation of the output data DOUT is represented by A, when the input data DIN toggles between logic value xe2x80x9c0xe2x80x9dand xe2x80x9c1xe2x80x9d. As the input data DIN toggles between logic xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, the output data DOUT voltage transitions between a high voltage level VOH=Vtermxe2x88x92A and a low voltage level VOL=Vtermxe2x88x92I*Rterm+A. As further shown, the logic state of the output data DOUT is determined based on the voltage level of the output data DOUT in relation to a reference voltage Vref. When the output data DOUT exceeds the reference voltage Vref, the output data DOUT is recognized as a logic xe2x80x9c0xe2x80x9d; and when the output data DOUT is less than the reference voltage Vref, the output data DOUT is recognized as a logic xe2x80x9c1xe2x80x9d.
When the input data DIN is two successive xe2x80x9c1xe2x80x9d, the channel attenuation of the output data DOUT reduces to Axe2x88x92xcex941 due to the increased turn-on time of the NMOS transistor MN. This causes an increase in the transition time, which is the time for the output data DOUT to transition above or below the reference voltage Vref when changing from one logic value to another.
FIG. 2(b) illustrates a voltage variation xcex942 of the output data DOUT caused by ISI when the input data DIN transitions from three successive logic xe2x80x9c1xe2x80x9ds to xe2x80x9c0xe2x80x9d. The channel attenuation Axe2x88x92xcex942 of the output data DOUT in this situation is even less than the case of transitioning from two successive xe2x80x9c1xe2x80x9ds to xe2x80x9c0xe2x80x9d. The lengthening of the transition time T1 during toggling of the input data DIN to the transition time T2 in this instance demonstrates the amount of skew that occurs in the voltage of the output data DOUT as a result of the ISI.
FIG. 3(a) illustrates a voltage variation xcex941 of the output data DOUT cause by ISI when the input data DIN transitions from two successive logic xe2x80x9c0xe2x80x9ds to xe2x80x9c1xe2x80x9d. As stated before, when the input data DIN toggles between logic value xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, the channel attenuation of the output data DOUT is A so that the high voltage level of the output data DOUT is VOH=Vtermxe2x88x92A and the low voltage level of the output data DOUT is VOL=Vtermxe2x88x92I*Rterm+A. When the input data DIN is two successive xe2x80x9c0xe2x80x9ds, the channel attenuation of the output data DOUT reduces to Axe2x88x92xcex941 due to the increased turn-off time of the NMOS transistor MN. Consequently, the transition time of the output data DOUT is skewed in a manner similar to that discussed above with respect to FIG. 2(a).
FIG. 3(b) illustrates a voltage variation xcex942 of the output data DOUT caused by ISI when the input data DIN transitions from three successive logic xe2x80x9c0xe2x80x9ds to xe2x80x9c1xe2x80x9d. The channel attenuation Axe2x88x92xcex942 of the output data DOUT is even less than the case of the transition from two successive logic xe2x80x9c0xe2x80x9ds to xe2x80x9c1xe2x80x9d due to the increased turn-off time of the NMOS transistor MN. Consequently, the transition time of the output data DOUT is skewed in a manner similar to that discussed above with respect to FIG. 2(b).
In the present invention, the open drain type output buffer includes a control circuit that detects the potential for skew in transition time of the output data and controls a driver circuit to mitigate against the skew.
In one exemplary embodiment, the driving circuit includes a first driver and at least one secondary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary driver has first and second states. The secondary driver pulls the output node towards the low voltage when in the first state, but does not pull the output node towards the low voltage in the second state. The control circuit determines when at least two consecutive low voltage output data at an output node have been generated, and controls the secondary driver such that the secondary driver is in the second state when the control circuit determines at least two consecutive low voltage output data have been generated.
In another exemplary embodiment, the driving circuit includes a first driver and at least one secondary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary driver has first and second states. The secondary driver pulls the output node towards the low voltage when in the first state, but does not pull the output node towards the low voltage in the second state. The control circuit determines when a transition from a steady high voltage output data to a low voltage output data occurs at an output node and controls the secondary driver such that the secondary driver is in the first state when the transition is determined.
A further embodiment of the invention combines the features of above-described embodiments.